1. Field of the Invention
The present invention relates to a negatively delayed signal generating circuit, and more particularly to an improved negatively delayed signal generating circuit for compensating a duty rate of an input signal.
2. Description of the Background Art
FIG. 1 is a circuit view illustrating a negatively delayed signal generating circuit according to the background art.
As shown therein, the negatively delayed signal generating circuit includes a pulse generator 10 for receiving an input signal CKIN and generating a oneshot pulse signal S1. A first delay unit 11 delays the oneshot pulse signal S1 and outputs a delayed oneshot pulse signal S2. A forward delay unit 12 includes a plurality of delay units for sequentially delaying the delayed oneshot pulse signal 32 output from the first delay unit 11. A mirror control unit 13 includes a plurality of NAND gates for respectively NANDing the oneshot pulse signal S1 and the sequentially delayed oneshot pulse signals, for example S3, output from the plurality of delay units in the forward delay unit 12, thereby outputting signals, for example, a signal S4. A backward delay unit 14 sequentially delays the output signal of the mirror control unit 13 and outputs a signal S5. A dummy load unit 15 receives output signals of the backward delay unit 14 and a ground voltage. A second delay unit 16 delays the output signal S5 of the backward delay unit 14 and outputs a negatively delayed signal CKO.
The pulse generator 10 includes an inverter I1 for inverting the input signal CKIN, a NAND gate ND1 for NANDing the input signal CKIN and the output signal of the inverter 11, and an inverter 12 for inverting the output signal of the NAND gate ND1.
The first delay unit 11 includes inverters 13,14 and buffers B1, B2 which are serially connected with one another.
The forward delay unit 12 includes a plurality of delay units D1, D2, . . . , D6 which are serially connected with one another. The delay unit D1 is provided with a NAND gate ND2 for NANDing the output signal S2 of the first delay unit 11 and a source voltage Vcc, and an inverter 15 for inverting the output signal of the NAND gate ND2. Also, the other delay units D2, D3, . . . , D6 are respectively identical to the first delay unit D1 in composition.
The mirror control unit 13 includes a plurality of NAND gates ND3, ND4, . . . , ND8, each of which NANDs the output signal S1 of the pulse generator 10 and a corresponding one of the output signals of the plurality of delay units D1, D2, . . . , D6 in the forward delay unit 12, thereby outputting the signals which are locked, for example, the signal S4.
The backward delay unit 14 includes a plurality of delay units D7, D8, . . . , D12 for sequentially delaying signals output from the mirror control unit 13. For example, the delay unit D12 includes a NAND gate ND9 and an inverter 16 to delay the output signal of the NAND gate ND8 in the mirror control unit 13, and output its delayed signal to the subsequent delay unit D11. Also, the other delay units D7, D8, . . . , D11 are respectively identical to the delay unit D12 in composition.
The dummy load unit 15 includes a plurality of NAND gates ND10A, ND10B, . . . , ND10F for respectively NANDing a corresponding one of the output signals of the delay units D7, D8, . . . , D12 in the backward delay unit 14 and a ground voltage.
The second delay unit 16 includes inverters 17, 18 for sequentially delaying the output signal of the backward delay unit 13.
With reference to FIGS. 2A through 2G illustrating timing diagrams of respective signals in the circuit of FIG. 1, the conventional negatively delayed signal generating circuit will now be described.
The pulse generator 10 that receives the input signal CKIN shown in FIG. 2A generates the oneshot pulse signal S1 in FIG. 2B having a pulse width PW1 and delayed as much as t1 by the inverters 11, 12, and outputs the generated oneshot pulse signal S1 to the first delay unit 11 and the mirror control unit 13.
The first delay unit 11 receives the oneshot pulse signal S1 and outputs the pulse signal S2 in FIG. 2C delayed as much as t2 to the forward delay unit 12.
Then, the plurality of delay units D1, D2, . . . , D6 in the forward delay unit 12 respectively, sequentially delay the output signal S2 of the first delay unit 11 as much as t3 to output the signal S2 in FIG. 2C.
When the oneshot pulse signal S1 of the pulse generator 10 and the respective output signals of the plurality of delay units D1, D2, . . . , D6 are in high levels at the same time, the respective NAND gates ND3, ND4, . . . , ND8 in the mirror control unit 13 respectively output a locked signal, for example, the signal S4 in FIG. 2E to the backward delay unit 14. Then, the backward delay unit 14 sequentially delays the locked signal and outputs the signal S5 in FIG. 2F to the second delay unit 16. The second delay unit 16 receives the signal S5 from the backward delay unit 14 and outputs the output signal CKO in FIG. 2G delayed as much as t4 compared to the signal S3 of the forward delay unit 12.
Therefore, the output signal CKO is converted to a locking signal during first and second cycles T1, T2 with regard to the input signal CK1, thereby becoming a negatively delayed signal slightly faster than a third pulse of the signal S1 in FIG. 2B beginning a third cycle T3.
Here, in order to generate the output signal CKO with its frequency larger than that of the input signal CKIN in the conventional negatively delayed signal generating circuit, respective rising and falling edges of the input signal CKIN need to be used. However, when the duty rate of the input signal is irregular, the duty rate of the negatively delayed signal also becomes irregular, whereby the conventional negatively delayed signal generating circuit for outputting the negatively delayed signal with its frequency larger than that of the input signal by detecting the rising and falling edges of the input signal is not applicable to a system that requires a high speed internal signal.